pUSRES1 is embedded with Wiznet W5500 chip which uses hardware logic gate circuits to implement the transport layer and network layer of TCPIP protocol stack such as TCP UDP ICMP IPv4 ARP IGMP PPPoE etc and integrates data link layer physical layer and 32K bytes of onchip RAM as data transmission and reception cache Enable the main control chip of the upper computer to only handle the processing tasks of TCPIP application layer control information This greatly saves the workload of the upper computer in data replication protocol processing and interrupt handling and improves system utilization and reliability nbsp nbsp nbsp During the operation users can approximately use W5500 as a peripheral RAM for MCU which is very simple The external interface of W5500 is a universal 80MHz highspeed SPI which can be used to expand highspeed Ethernet solutions on different platforms Automatic negotiation LED status display SPI interface has fast speed and high stability nbsp nbsp nbsp Size and pin compatibility with Wiznets official module WIZ820io nbsp nbsp Note This module is not an SPI to Ethernet transparent transmission module and requires an external microcontroller for use Users need to understand the usage of the W5500 chip Provide example code for STM32 p